A variety of electronic circuits require the synthesis of extremely accurate clock signals at a precise frequency. One way of achieving this result is to lock a digital phase-locked loop employing a software digital controlled oscillator (SDCO) to generate phase and frequency values from a reference signal, which after suitable conversion, drive a hardware digital or numerical controlled oscillator (DCO/NCO), referred to hereafter as a DCO. This comprises an accumulator that increments by a certain amount on each system pulse. When the accumulator overflows, it generates a carry output, which represents the output pulse. The remainder left in the accumulator when a carry is output represents the phase. The DCO produces clock pulses at the desired overall frequency, but since these pulses are coincident with the system pulses when the carry occurs, they are not generally correctly phased and form a so-called gapped clock signal because when there is no carry no output occurs on some of the system clock pulses.
A digital-to-time converter (DTC) makes use of the phase information provided by the remainder to interpolate the output of the hardware DCO and produce evenly spaced clock pulses in their correct phase locations. Such an arrangement is described in U.S. Pat. No. 8,692,599, the contents of which are herein incorporated by reference.
A problem arises in the prior art due to the fact that the DTC, which is implemented in analog form, is not perfectly linear. The non-linear space between the interpolation points in each system clock pulse period creates output clock jitter that is significantly larger than the resolution of the DTC interpolation as determined by the number M of interpolation points k. Pre-calibration is generally used to eliminate this non-linear distortion, but this has to be constantly adjusted to compensate for temperature variations.